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18-mbit 4-word burst sram with ddr-i ar c hi tectu r e CY7C1323BV25 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05631 rev. *a revised april 3, 2006 features ? 18-mbit density (512 kbit x 36) ? 167-mhz clock for high bandwidth ? 4-word burst for reducing address bus frequency ? double data rate (ddr) interfaces (data transferred at 333 mhz @ 167 mhz) ? two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only ? two input clocks for output data (c and c ) to minimize clock-skew an d flight-time mismatches. ? separate port selects for depth expansion ? synchronous internally self-timed writes ? 2.5v core power supply with hstl inputs and outputs ? available in 165-ball fbga package (13 x 15 x 1.4 mm) ? variable drive hstl output buffers ? expanded hstl output voltage (1.4v?1.9v) ? jtag 1149.1 compatible test access port configuration CY7C1323BV25 - 256k x 36 functional description the CY7C1323BV25 is a 2.5v synchronous pipelined sram equipped with ddr-i (double data rate) architecture. the ddr - i architecture consists of an sram core with advanced synchronous peripheral circuitry and a 2-bit burst counter. addresses for read and write are latched on alternate rising edges of the input (k) clock. write data is registered on the rising edges of both k and k . read data is driven on the rising edges of c and c if provided, or on the rising edge of k and k if c/c are not provided. every read or write operation is associated with four words that burst sequentially into or out of the device. the burst counter takes in the least two signif- icant bits of the external address and bursts four 36-bit words. depth expansion is accomplished with port selects for each port. port selects allow each port to operate independently. asynchronous inputs include impedance match (zq). synchronous data outputs (q, sharing the same physical pins as the data inputs d) are tightly matched to the two output echo clocks cq/cq , eliminating the need for separately capturing data from each individual ddr sram in the system design. output data clocks(c/c ) are also provided for maximum system clocking and data sy nchronization flexibility. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. clk a (18:0) gen. k k control logic address register read add. decode read data reg. r/w dq [35:0] output logic reg. reg. reg. 72 36 144 36 bws [3:0] vref write add. decode write reg 72 19 c c 512k x 36 array write reg write reg write reg 36 ld control burst logic a (1:0) a (18:2) 17 cq cq logic block diagram (CY7C1323BV25)
CY7C1323BV25 document #: 38-05631 rev. *a page 2 of 18 selection guide 167 mhz unit maximum operating frequency 167 mhz maximum operating current 700 ma pin configuration pin definitions name i/o description dq [35:0] input/output- synchronous data input/output signals . inputs are sampled on the rising edge of k and k clocks during valid write operations. these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations or k and k when in single clock mode. when read access is deselected, q [35:0] are automatically three-stated. ld input- synchronous synchronous load . this input is brought low when a bus cycle sequence is to be defined. this definition includes addre ss and read/write direction. all transactions operate on a burst of 4 data (two clock periods of bus activity). bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2 and 3 ? active low. sampled on the rising edge of the k and k clocks during write operations. used to sele ct which byte is writ ten into the device during the current portion of the write operations. bytes not written remain unaltered. CY7C1323BV25 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27] all the byte write selects are sampled on the same edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written into the device. a, a0, a1 input- synchronous address inputs. these address inputs are multiplexed for both read and write opera- tions. a0 and a1 are the inputs to the burst counter . these are incremented in a linear fashion internally. 19 address inputs are needed to access the entire memory array. all the address inputs are ignor ed when the part is deselected. r/w input- synchronous synchronous read/write input . when ld is low, this input designates the access type (read when r/w is high, write when r/w is low) for loaded address. r/w must meet the set-up and hold times around edge of k. 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc nc nc gnd/144m nc/36m bws 2 k r/w bws 1 dq27 dq18 nc nc nc tdo nc nc dq31 nc nc nc tck nc dq28 a bws 3 k bws 0 vss aa0a1 dq19 vss vss vss vss vdd a vss vss vss vdd dq20 dq21 vddq dq32 dq23 dq34 dq25 dq26 a vddq vss vddq vdd vdd dq22 vddq vdd vddq vdd vddq vdd vss vdd vddq vddq vss vss vss vss a a c vss a a a dq29 vss nc vss dq30 nc vref vss vdd vss vss a vss c nc dq33 nc dq35 dq24 vdd a 891011 dq0 a gnd/72m ld cq a nc nc dq8 vss nc dq17 dq7 nc vss nc dq6 dq14 nc nc vref nc dq3 vddq nc vddq nc dq5 vddq vddq vddq dq4 vddq nc dq13 nc vddq vddq nc vss nc dq1 nc tdi tms vss a nc a dq16 dq15 nc zq dq12 dq2 dq10 dq11 dq9 nc a CY7C1323BV25 (256k 36) 165-ball fbga (13 x 15 x 1.4 mm) pinout
CY7C1323BV25 document #: 38-05631 rev. *a page 3 of 18 introduction functional overview the CY7C1323BV25 is a synchronous pipelined burst sram equipped with ddr interface. accesses are initiated on the po sitive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the rising edge of output clocks (c and c or k and k when in single clock mode). all synchronous data inputs (d [35:0] ) pass through input registers controlled by th e input clocks (k and k ). all synchronous data outputs (q [35:0] ) pass through output registers controlled by the ri sing edge of the output clocks (c and c or k and k when in single clock mode). all synchronous control (r/w , ld , bws 0 , bws 1, bws 2 , bws 3 ) inputs pass through input registers controlled by the rising edge of the in put clocks (k and k ). read operations the CY7C1323BV25 is organized internally as an array of 512k x 36. accesses are completed in a burst of four sequential 36-bit data words. read operations are initiated by asserting r/w high and ld low at the rising edge of the positive input clock (k). the address presented to address inputs are stored in the read address register and the least two significant bits of the a ddress are presented to the burst counter. the burst counter increments the address in a linear fashion. following the next k clock rise the corresponding 36-bit word of data from this address location is driven onto the q [35:0] using c as the output timing reference. on the subse- c input-clock positive input clo ck for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. c input-clock negative input clock for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board cack to the controller. see application example for further details. k input-clock positive input clock input. the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [35:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input-clock negative input clock input. k is used to capture synchronous inputs being presented to the device and to drive out data through q [35:0] when in single clock mode. cq echo clock cq is referenced with respect to c . this is a free running clock and is synchronized to the output clock (c) of the ddr-i. in the single clock mode, cq is generated with respect to k. the timings for the echo clocks are shown in the ac timing table. cq echo clock cq is referenced with respect to c . this is a free running clock and is synchronized to the output clock (c) of the d dr-i. in the single clock mode, cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. zq input output impedance matching input. this input is used to tune the device outputs to the system data bus impedance. cq, cq and q [35:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. tdo output tdo for jtag. tck input tck pin for jtag. tdi input tdi pin for jtag. tms input tms pin for jtag. nc n/a not connected to the die. can be tied to any voltage level. nc/36m n/a address expansion for 36m. this is not connected to the die. gnd/72m input address expansion for 72m. this should be tied low. gnd/144m input address expansion for 144m. this should be tied low. v ref input- reference reference voltage input. static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device. v ss ground ground for the device. v ddq power supply power supply inputs for the outputs of the device. pin definitions (continued) name i/o description
CY7C1323BV25 document #: 38-05631 rev. *a page 4 of 18 quent rising edge of c the next 36-bit data word from the address location generated by the burst counter is driven onto the q [35:0] . this process continues until all four 36-bit data words have been driven out onto q [35:0] . the requested data will be valid 3 ns from the rising edge of the output clock (c or c , 167 mhz device). in order to maintain the internal logic, each read access must be allo wed to complete. each read access consists of four 36-bit data words and takes 2 clock cycles to complete. therefore, read accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device will ignore the second read request. read accesses can be initiated on every other k clock rise. doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (c and c or k and k when in single clock mode). when the read port is deselected, the CY7C1323BV25 will first complete the pending read transactions. synchronous internal circuitry will automatically thre e-state the outputs following the next rising edge of the positive output clock (c). this will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are initiated by asserting r/w low and ld low at the rising edge of the positive input clock (k). the address presented to address inputs are stored in the write address register and the least two significant bits of the address are presented to the burs t counter. the burst counter increments the address in a linear fashion. on the following k clock rise the data presented to d [35:0] is latched and stored into the 36-bit write data register provided bws [3:0] are asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [35:0] is also stored into the write data register provided bws [3:0] are asserted active. this proce ss continues for one more cycle until four 36-bit words (a total of 144 bits) of data are stored in the sram. the 144 bits of data are then written into the memory array at the specifie d location. therefore, write accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device will ignore the second write request. write accesses can be initiated on every other rising edge of the positive input clock (k). doing so will pipeline the data flow such that 36-bits of data can be transferred into the device on every rising edge of the input clocks (k and k ). when deselected, the write port will ignore all inputs after the pending write operations have been completed. byte write operations byte write operations are supported by the CY7C1323BV25. a write operation is initiated as described in the write operation section above. the bytes that are written are deter- mined by bws [3:0] which are sampled with each set of 36-bit data word. asserting the appropriate byte write select input during the data portion of a write will allow the data being presented to be latched and written into the device. deasserting the byte write select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. this feat ure can be used to simplify read/modify/write operations to a byte write operation. single clock mode the CY7C1323BV25 can be used with a single clock that controls both the input and output registers. in this mode the device will recognize only a single pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, the user must tie c and c high at power on. this function is a strap option and not alterable during device operation. ddr operation the CY7C1323BV25 enables high performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. at slower frequencies, the CY7C1323BV25 requires a single no operation (nop) cycle when tran sitioning from a read to a write cycle. at higher frequencies, a second nop cycle may be required to prevent bus contention. if a read occurs after a write cycle, address and data for the write are stored in registers. the write information must be stored because the sram can not perform the last word write to the array without conflicting with the read. the data stays in this register until the next write cycle occurs. on the first write cycle after the read(s), the stored data from the earlier write will be written into the sram array. this is called a posted write. depth expansion depth expansion require s replicating the ld control signal for each bank. all other control signals can be common between banks as appropriate. echo clocks echo clocks are provided on the ddr-i to simplify data capture on high-speed systems. two echo clocks are generated by the ddr-i. cq is referenced with respect to c and cq is refer- enced with respect to c . these are free-running clocks and are synchronized to the output clock of the ddr-i. in the single clock mode, cq is generated with respect to k and cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. programmable impedance an external resistor, rq mu st be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the va lue of rq must be 5x the value of the intended line impedance driven by the sram, the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq =1.5v. the output impedance is adjusted every 1024 cycles to adjust for drifts in supply voltage and temperature.
CY7C1323BV25 document #: 38-05631 rev. *a page 5 of 18 application example [1] truth table [2, 3, 4, 5, 6, 7] operation k ld r/w dq dq dq dq write cycle: load address; wait one cycle; input write data on 2 consecutive k and k rising edges. l-h l l [8] d(a1) at k(t+1) d(a2) at k (t+1) d(a3) at k(t+2) d(a4) at k (t+2) read cycle: load address; wait one cycle; read data on 2 consecutive c and c rising edges. l-h l h [9] q(a1) at c(t+1) q(a2) at c (t+1) q(a3) at c(t+2) q(a4) at c (t+2) nop: no operation l-h h x high-z high-z high-z) high-z standby: clock stopped stopped x x previous state previous state previous state previous state linear burst address table first address (external) second address (internal) third address (internal) fourth address (internal) x..x00 x..x01 x..x10 x..x11 x..x01 x..x10 x..x11 x..x00 x..x10 x..x11 x..x00 x..x01 x..x11 x..x00 x..x01 x..x10 notes: 1. the above application shows 2 ddr-i being used. 2. x = ?don't care?, h = logic high, l = logic low , represents rising edge. 3. device will power-up deselected and the outputs in a three-state condition. 4. ?a1? represents address location latche d by the devices when transaction was init iated. a2, a3 and a4 represents the internal address sequence in the burst. 5. ?t? represents the cycle at which a read/write operation is st arted. t+1 and t+2 are the first and second clock cycles succee ding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c when clock is stopped. this is not essential, but permits mo st rapid restart by overcoming transmission line charging symmetrically. 8. this signal was high on previous k clock rise. initiating co nsecutive write operations on consecutive k clock rises is not pe rmitted. the device will ignore the second write request. 9. this signal was low on previous k clock rise. initiating cons ecutive read operations on consec utive k clock rises is not perm itted. the device will ignore the second read request. ld# vterm = 0.75v vterm = 0.75v cc# r/w# zq cq/cq# k# dq a k ld# c c# r/w# zq cq/cq# k# dq a k bus master (cpu or asic) sram#1 sram#2 dq addresses cycle start# r/w# return clk source clk return clk# source clk# e cho clock1/echo clock#1 e cho clock2/echo clock#2 r = 50 ohms r = 250 ohms r = 250ohms
CY7C1323BV25 document #: 38-05631 rev. *a page 6 of 18 write cycle descriptions [2, 10] bws 0 bws 1 bws 2 bws 3 kk comments lllll-h-during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. llll-l-hduring the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l-h - during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. l h h h - l-h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. h l h h l-h - during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h l h h - l-h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h h l h l-h - during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h l h - l-h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h h l l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. h h h l - l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. h h h h l-h - no data is written into the device during this portion of a write operation. h h h h - l-h no data is written into the device during this portion of a write operation. note: 10. assumes a write cycle was initiated per the write port cycle description truth table. bws 0 , bws 1 , bws 2 , bws 3 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
CY7C1323BV25 document #: 38-05631 rev. *a page 7 of 18 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-1900. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is ac tive depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected betw een the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register s. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. seve ral no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr st ate. the idcode instruction
CY7C1323BV25 document #: 38-05631 rev. *a page 8 of 18 is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructi ons are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the captur e-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sampl e/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system out put pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that t he tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the ?extest output bus tri-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bu s pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
CY7C1323BV25 document #: 38-05631 rev. *a page 9 of 18 tap controller state diagram [11] note: 11. the 0/1 next to each state represents the value at tms at the rising edge of tck. test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
CY7C1323BV25 document #: 38-05631 rev. *a page 10 of 18 tap controller block diagram tap electrical characteristics over the operating range [12, 15, 17] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma 1.7 v v oh2 output high voltage i oh = ? 100 a2.1 v v ol1 output low voltage i ol = 2.0 ma 0.7 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 1.7 v dd + 0.3 v v il input low voltage ?0.3 0.7 v i x input and output load current gnd v i v ddq ?5 5 a tap ac switching characteristics over the operating range [13, 14] parameter description min. max. unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 20 ns t tl tck clock low 20 ns set-up times t tmss tms set-up to tc k clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns notes: 12. these characteristics pertain to the tap inputs (tms, tck, td i and tdo). parallel load levels are specified in the electrica l characteristics table. 13. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 14. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns. 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms
CY7C1323BV25 document #: 38-05631 rev. *a page 11 of 18 output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions [14] tap ac switching characteristics over the operating range (continued) [13, 14] parameter description min. max. unit (a) tdo c l = 20 pf z 0 = 50 ? gnd 1.25v test clock test mode select tck tms test data-in tdi test data-out tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov 50 ? 2.5v 0v all input pulses 1.25v identification register definitions instruction field value description CY7C1323BV25 revision number (31:29) 000 version number. cypress device id (28:12) 01011111011100110 defines the type of sram. cypress jedec id (11:1) 00000110100 allows unique identification of sram vendor. id register presence (0) 1 indicate the presence of an id register.
CY7C1323BV25 document #: 38-05631 rev. *a page 12 of 18 scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input/output ring contents. idcode 001 loads the id register with the vendor id code and places the regist er between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/out put contents. places the boundar y scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instru ction is reserved for future use. sample/preload 100 captures the input/o utput ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instru ction is reserved for future use. reserved 110 do not use: this instru ction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
CY7C1323BV25 document #: 38-05631 rev. *a page 13 of 18 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 27 11h 54 7b 81 3g 1 6p 28 10g 55 6b 82 2g 2 6n 29 9g 56 6a 83 1j 3 7p 30 11f 57 5b 84 2j 4 7n 31 11g 58 5a 85 3k 5 7r 32 9f 59 4a 86 3j 6 8r 33 10f 60 5c 87 2k 7 8p 34 11e 61 4b 88 1k 8 9r 35 10e 62 3a 89 2l 9 11p 36 10d 63 1h 90 3l 10 10p 37 9e 64 1a 91 1m 11 10n 38 10c 65 2b 92 1l 12 9p 39 11d 66 3b 93 3n 13 10m 40 9c 67 1c 94 3m 14 11n 41 9d 68 1b 95 1n 15 9m 42 11b 69 3d 96 2m 16 9n 43 11c 70 3c 97 3p 17 11l 44 9b 71 1d 98 2n 18 11m 45 10b 72 2c 99 2p 19 9l 46 11a 73 3e 100 1p 20 10l 47 internal 74 2d 101 3r 21 11k 48 9a 75 2e 102 4r 22 10k 49 8b 76 1e 103 4p 23 9j 50 7c 77 2f 104 5p 24 9k 51 6c 78 3f 105 5n 25 10j 52 8a 79 1g 106 5r 26 11j 53 7a 80 1f
CY7C1323BV25 document #: 38-05631 rev. *a page 14 of 18 maximum ratings (above which the useful life may be impaired.) storage temperature .................................... ? 65c to + 150c ambient temperature with power applied ................................................. ? 55c to + 125c supply voltage on v dd relative to gnd ........? 0.5v to + 3.6v supply voltage on v ddq relative to gnd ......? 0.5v to + v dd dc applied to outputs in high-z ...........? 0.5v to v ddq + 0.5v dc input voltage [15] .................................. ? 0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature (t a )v dd [16] v ddq [16] com?l 0 c to + 70 c 2.5 0.1v 1.4v to 1.9v ind?l ?40c to + 85c electrical characteristics over the operating range [17] dc electrical characteristics parameter description test conditions min. typ. max. unit v dd power supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage 1.4 1.5 1.9 v v oh output high voltage note 18 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 19 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage [15] v ref + 0.1 v ddq + 0.3 v v il input low voltage [15, 20 ] ?0.3 v ref ? 0.1 v i x input leakage current gnd v i v ddq ?5 5 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a v ref input reference voltage [21] typical value = 0.75v 0.68 0.75 0.95 v i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 700 ma i sb1 automatic power-down max. v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc, inputs static 450 ma ac input requirements parameter description test conditions min. typ. max. unit v ih input high voltage v ref + 0.2 ? ? v v il input low voltage ? ? v ref ? 0.2 v thermal resistance [22] parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 16.7 c/w jc thermal resistance (junction to case) 2.5 c/w notes: 15. overshoot: v ih (ac) < v ddq + 0.85v (pulse width less than t cyc /2). undershoot: v il (ac) > ?1.5v (pulse width less than t cyc /2). 16. power-up: assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 17. all voltage referenced to ground. 18. output are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? <= rq <= 350 ? . 19. output are impedance controlled. i ol =(v ddq /2)/(rq/5) for values of 175 ? <= rq <= 350 ? s. 20. this spec is for all inputs except c and c clock. for c and c clock, v il (max.) = v ref ? 0.2v. 21. v ref ( min .) = 0.68v or 0.46v ddq , whichever is larger, v ref (max.) = 0.95v or 0.54v ddq , whichever is smaller. 22. tested initially and after any design or process change that may affect these parameters.
CY7C1323BV25 document #: 38-05631 rev. *a page 15 of 18 capacitance [22] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 2.5v v ddq = 1.5v 5pf c clk clock input capacitance 6 pf c o output capacitance 7 pf ac test loads and waveforms switching characteristics over the operating range [ 23 ] cypress parameter consortium parameter description 167 mhz unit min. max. t power [24] v cc (typical) to the first access read or write 10 s cycle time t cyc t khkh k clock and c clock cycle time 6.0 ns t kh t khkl input clock (k/k and c/c ) high 2.4 ns t kl t klkh input clock (k/k and c/c ) low 2.4 ns t khk h t khk h k/k clock rise to k /k clock rise and c/c to c/c rise (rising edge to rising edge) 2.8 3.2 ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 2.0 ns set-up times t sa t sa address set-up to clock (k and k ) rise 0.7 ns t sc t sc control set-up to clock (k and k ) rise (rps , wps , bws 0 , bws 1 )0.7 ns t sd t sd d [35:0] set-up to clock (k and k ) rise 0.7 ns hold times t ha t ha address hold after clock (k and k ) rise 0.7 ns t hc t hc control signals hold after clock (k and k ) rise (rps , wps , bws 0 , bws 1 ) 0.7 ns t hd t hd d [35:0] hold after clock (k and k ) rise 0.7 ns notes: 23. unless otherwise noted, test conditions assume signal tran sition time of 2 v/ns, timing reference levels of 0.75v,v ref = 0.75v, rq = 250 ? , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. 24. this part has a voltage regulator that steps down the voltage internally; t power is the time power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 1.25v 0.25v r = 50 ? 5pf all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75v v ref = 0.75v [23] 0.75v under te s t 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ?
CY7C1323BV25 document #: 38-05631 rev. *a page 16 of 18 output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid 3.0 ns t doh t chqx data output hold after output c/c clock rise (active to active) 0.8 ns t chz t chz clock (c and c ) rise to high-z (active to high-z) [25, 26] 3.0 ns t clz t clz clock (c and c ) rise to low-z [25, 26] 0.8 ns t ccqo t chcqv c/c clock rise to echo clock valid 0.8 3.2 ns t cqd t cqhqv echo clock high to data valid 0.40 ns t cqdoh t cqhqx echo clock high to data invalid ?0.40 ns t cqhz t chz clock (cq and cq ) rise to high-z (active to high-z) [25, 26] 0.40 ns t cqlz t clz clock (cq and cq ) rise to low-z [25, 26] ?0.40 ns switching waveforms [27, 28, 29] notes: 25. t chz , t clz , are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is m easured 100 mv from steady-st ate voltage. 26. at any given voltage and temperature t chz is less than t clz and, t chz less than t co . 27. q01 refers to output from address a0. q02 refers to output from the next internal burst address following a0, i.e., a0+1. 28. output are disabled (high-z) one clock cycle after a nop. 29. in this example, if address a4 = a3, then data q41 = d31, q42 = d32, q43 = d33, and q44 = d34. write data is forwarded immed iately as read results.this note applies to the whole diagram. switching characteristics over the operatin g range (continued) [ 23 ] cypress parameter consortium parameter description 167 mhz unit min. max.
CY7C1323BV25 document #: 38-05631 rev. *a page 17 of 18 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. ordering information ?not all of the speed, package and temperature ranges are available. please contact your local sales representative or visit www.cypress.com for actual products offered?. speed (mhz) ordering code package diagram package type operating range 167 CY7C1323BV25-167bzc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial CY7C1323BV25-167bzxc 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead free CY7C1323BV25-167bzi 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial CY7C1323BV25-167bzxi 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead free package diagram a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25mcab ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin1corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 -0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a 165 fbga 13 x 15 x 1.40 mm bb165d/bw165d a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 - 0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a 165-ball fbga (13 x 15 x 1.4 mm) (51-85180)
CY7C1323BV25 document #: 38-05631 rev. *a page 18 of 18 document history page document title: CY7C1323BV25 18-mb 4-wo rd burst sram with ddr-i architecture document number: 38-05631 rev. ecn no. issue date orig. of change description of change ** 253050 see ecn syt new data sheet *a 436882 see ecn nxr converted from preliminary to final removed 133 mhz & 100 mhz from product offering included industrial operating range changed c/c description in the features section & pin description table. changed t tcyc from 100 ns to 50 ns, changed t tf from 10 mhz to 20 mhz and changed t th and t tl from 40 ns to 20 ns in tap ac switching characteristics table modified the zq pin definition as follows: alternately, this pin can be connected directly to v ddq , which enables the minimum impedance mode included maximum ratings for supply voltage on v ddq relative to gnd changed the maximum ratings for dc input voltage from v ddq to v dd modified the description of i x from input load current to input leakage current on page # 14 modified test condition in note# 16 from v ddq < v dd to v ddq v dd updated the ordering information table and replaced the package name column with package diagram

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